WM2639 12-bit parallel input voltage output dac with internal reference production data, july 1999, rev 1.0 wolfson microelectronics ltd lutton court, bernard terrace, edinburgh, eh8 9nx, uk tel: +44 (0) 131 667 9386 fax: +44 (0) 131 667 5176 email: sales@wolfson.co.uk http://www.wolfson.co.uk production data contain final specifications current on publication date. supply of products conforms to wolfson microelectronics? terms and conditions.. master 15/07/99 15:02 1999 wolfson microelectronics ltd . features 12-bit voltage output dac single supply 2.7v to 5.5v operation dnl 0.3 lsbs, inl 1.2 lsbs internal programmable voltage reference settling time 1 m m s typical 12-bit microprocessor compatible interface power down mode 10na applications battery powered test instruments digital offset and gain adjustment battery operated/remote industrial controls machine and motion control devices wireless telephone and communication systems speech synthesis arbitrary waveform generation mass storage devices ordering information device temp. range package WM2639cdt 0 to 70 c 20-pin tssop WM2639idt -40 to 85 c 20-pin tssop description the WM2639 is a 12-bit voltage output, resistor string, digital-to- analogue converter. a hardware controlled power down mode is provided that reduces current consumption to 10na. the device has been designed to interface efficiently to industry standard microprocessors and dsps. the WM2639 features an internal programmable voltage reference simplifying overall system design. the reference voltage can also be supplied externally. excellent performance is delivered with a typical dnl of 0.3 lsbs and typical inl of 1.2 lsbs. the output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a class a output stage (slow mode, class ab). the 12 data bits are double buffered enabling the output to be asynchronously updated under hardware control. the settling time of the dac is software programmable to allow the designer to optimise speed versus power dissipation. the device is available in a 20-pin tssop package. commercial temperature (0 to 70c) and industrial temperature (-40 to 85c) variants are supported. block diagram typica l performance (13) out data ref(12) power-on reset d[0-11] (19,20, 1-10) nwe (17) (14) gnd powerdown control reference input buffer WM2639 x1 x2 dac output buffer ncs (18) 12-bit dac latch 12-bit input register 2-bit reference select latch 1.024v/2.048v selectable reference x1 reference output buffer with ouput enable v dd (11) (16) nldac 2-bit control latch reg (15) 5v = vdd, v ref -1 -0.8 -0.4 -0.2 0.2 0.4 0.8 1 512 1024 2048 2559 3583 4095 dnl - lsb
WM2639 production data wolfson microelectronics ltd production data rev 1.0 july 1999 2 pin configuration ncs 9 10 d10 d11 12 11 ref v dd 20 13 14 15 16 17 18 19 d1 agnd reg nldac nwe d0 out 8 1 2 3 4 5 6 7 d9 d3 d4 d5 d6 d7 d8 d2 pin description pin no name type description 1 d2 digital input data input. 2 d3 digital input data input. 3 d4 digital input data input. 4 d5 digital input data input. 5 d6 digital input data input. 6 d7 digital input data input. 7 d8 digital input data input. 8 d9 digital input data input. 9 d10 digital input data input. 10 d11 digital input data input.(msb) 11 vdd supply positive power supply. 12 ref analogue i/o analogue reference voltage input/output. 13 out analogue output dac analogue voltage output. 14 agnd supply analogue ground. 15 reg digital input register select. digital input used to access control register. 16 nldac digital input load dac. digital input active low. nldac must be taken low to update the dac latch from the holding latches. 17 nwe digital input write enable. digital input active low. 18 ncs digital input chip select. digital input active low. 19 d0 digital input data input. (lsb) 20 d1 digital input data input.
production data WM2639 wolfson microelectronics ltd production data rev 1.0 july 1999 3 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. condition min max digital supply voltages, vdd to gnd 7v reference input voltage -0.3v vdd + 0.3v digital input voltage range to gnd -0.3v vdd + 0.3v operating temperature range, t a WM2639cdt WM2639idt 0 c -40 c 70 c 85 c storage temperature -65 c 150 c lead temperature 1.6mm (1/16 inch) soldering for 10 seconds 260 c recommended operating conditions parameter symbol test conditions min typ max unit supply voltage vdd 2.7 5.5 v high-level digital input voltage v ih vdd = 2.7v to 5.5v 2 v low-level digital input voltage v il vdd = 2.7v to 5.5v 0.8 v reference voltage to ref v ref see note vdd - 1.5 v load resistance r l 2 k w load capacitance c l 100 pf WM2639cdt 0 70 c operating free-air temperature t a WM2639idt -40 85 c note : reference voltages greater than vdd/2 will cause output saturation for large dac codes.
WM2639 production data wolfson microelectronics ltd production data rev 1.0 july 1999 4 electrical characteristics test conditions: r l = 10k w , c l = 100pf. vdd = 5v 10%, v ref = 2.048v and vdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise) parameter symbol test conditions min typ max unit static dac specifications resolution 12 bits integral non-linearity inl see note 1 1.2 3 lsb differential non-linearity dnl see note 2 0.3 0.5 lsb zero code error zce see note 3 3 20 mv gain error ge see note 4 0.3 % fsr d.c. power supply rejection ratio dc psrr see note 5 0.5 mv/v zero code error temperature coefficient see note 6 20 ppm/ c gain error temperature coefficient see note 6 20 ppm/ c dac output specifications output voltage range 0 vdd - 0.4 v output load regulation 2k w to 10k w load see note 7 0.1 0.3 % power supplies active supply current i dd no load, v ih = vdd, v il = 0v vdd = 5v, v ref = 2.048v, internal slow fast vdd = 5v, v ref = 2.048v, external slow fast vdd = 3v, v ref = 1.024v, internal slow fast vdd = 3v, v ref = 1.024v, external slow fast see note 8 1.3 2.3 0.9 1.9 1.2 2.1 0.9 1.8 1.6 2.8 1.2 2.4 1.5 2.6 1.1 2.3 ma ma ma ma ma ma ma ma power down supply current no load, all inputs 0v or vdd see note 9 0.01 1 m a dynamic dac specifications slew rate dac code 32-4095, 10%-90% slow fast see note 10 1.2 6.0 1.7 10 v/ m s v/ m s settling time dac code 32-4095 slow fast see note 11 3.5 1 m s m s glitch energy code 2047 to 2048 5 nv-s
production data WM2639 wolfson microelectronics ltd production data rev 1.0 july 1999 5 test conditions: r l = 10k w , c l = 100pf. vdd = 5v 10%, v ref = 2.048v and vdd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise) parameter symbol test conditions min typ max unit signal to noise ratio snr fs = 480ksps, f out = 1khz, bw = 20khz, t a =25 c see note 12 73 78 db signal to noise and distortion ratio snrd fs = 480ksps, f out = 1khz, bw = 20khz, t a =25 c see note 12 61 67 db total harmonic distortion thd fs = 480ksps, f out = 1khz, bw = 20khz, t a =25 c see note 12 -69 -62 db spurious free dynamic range spfdr fs = 480ksps, f out = 1khz, bw = 20khz, t a = 25 c see note 12 63 74 db reference configured as input reference input resistance r refin 10 m w reference input capacitance c refin 55 pf reference feedthrough v ref = 1v pp at 1khz + 1.024vdc, dac code 0 -60 db reference input bandwidth v ref = 0.2v pp + 1.024v d.c. dac code 2048 slow fast 500 900 khz khz reference configured as output low reference voltage v refoutl 1.003 1.024 1.045 v high reference voltage v refouth vdd > 4.75v 2.027 2.048 2.069 v output source current i refsrc 1 ma output sink current i refsnk -1 ma load capacitance 100 pf psrr -48 db digital inputs high level input current i ih input voltage = vdd 1 m a low level input current i il input voltage = 0v -1 m a input capacitance c i 8 pf notes: 1. integral non-linearity (inl) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full scale errors). 2. differential non-linearity (dnl) is the difference between the measured and ideal 1lsb amplitude change of any adjacent two codes. a guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. 3. zero code error is the voltage output when the dac input code is zero. 4. gain error is the deviation from the ideal full scale output excluding the effects of zero code error. 5. power supply rejection ratio is measured by varying v dd from 4.5v to 5.5v and measuring the proportion of this signal imposed on the zero code error and the gain error. 6. zero code error and gain error temperature coefficients are normalised to full scale voltage. 7. output load regulation is the difference between the output voltage at full scale with a 10k w load and 2k w load. it is expressed as a percentage of the full scale output voltage with a 10k w load. 8. i dd is measured while continuously writing code 2048 to the dac. for v ih < v dd - 0.7v and v il > 0.7v supply current will increase. 9. typical supply current in power down mode is 10na. production test limits are wider for speed of test. 10. slew rate results are for the lower value of the rising and falling edge slew rates. 11. settling time is the time taken for the signal to settle to within 0.5lsb of the final measured value for both rising and falling edges. limits are ensured by design and characterisation, but are not production tested.
WM2639 production data wolfson microelectronics ltd production data rev 1.0 july 1999 6 12. snr, snrd, thd and spfdr are measured on a synthesised sinewave at frequency f out generated with a sampling frequency fs . serial interface d[0-11] reg ncs nwe nldac x x data reg x x t sud t sur t sucswe t hdr t whwe t suweld t wld figure 1 timing diagram test conditions: r l = 10k w , c l = 100pf. v dd = 5v 10%, v ref = 2.048v and v dd = 3v 10%, v ref = 1.024v over recommended operating free-air temperature range (unless noted otherwise) symbol test conditions min typ max unit t sucswe setup time ncs low before positive nwe edge 15 ns t sud setup time data ready before positive nwe edge 10 ns t sur setup time reg ready before positive nwe edge 20 ns t hdr data and reg hold after positive nwe edge 5 ns t suweld setup time nwe high before nldac low 5 ns t whwe high pulse width of nwe 20 ns t wld low pulse width of nldac 23 ns
production data WM2639 wolfson microelectronics ltd production data rev 1.0 july 1999 7 typical performance graphs 5v = vdd, v ref = external. 2.048v, speed = fast mode, load = 10k/100pf -3 -2 -1 0 1 2 3 0 512 1024 1536 2048 2559 3071 3583 4095 digital code inl - lsb figure 2 integral non-linearity 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 3.5 4 isink - ma vo - output voltage - v slow fast vdd = 3v, v ref = internal. 1v, input code = 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 isink - ma vo - output voltage - v slow fas) vdd = 5v, v ref = int. 2v, input code = 0 figure 3 sink current vdd = 3v figure 4 sink current vdd = 5v 2.035 2.0355 2.036 2.0365 2.037 2.0375 2.038 2.0385 2.039 2.0395 0 0.5 1 1.5 2 2.5 3 3.5 4 isource - ma vo - output voltage - v slow fast vdd = 3v, v ref = int. 1v, input code = 4095 4.075 4.0755 4.076 4.0765 4.077 4.0775 4.078 4.0785 4.079 4.0795 0 0.5 1 1.5 2 2.5 3 3.5 4 isource - ma vo - output voltage - v slow fast vdd = 5v, v ref = int. 2v, input code = 409 5 figure 5 source current vdd = 3v figure 6 source current vdd = 5v
WM2639 production data wolfson microelectronics ltd production data rev 1.0 july 1999 8 device description general function the device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see block diagram). the output voltage is determined by the reference input voltage and the input code according to the following relationship: output voltage = ( ) 4096 code v 2 ref input output 1111 1111 1111 ( ) 4096 4095 v 2 ref : : 1000 0000 0001 ( ) 4096 2049 v 2 ref 1000 0000 0000 ( ) ref ref v 4096 2048 v 2 = 0111 1111 1111 ( ) 4096 2047 v 2 ref : : 0000 0000 0001 ( ) 4096 1 v 2 ref 0000 0000 0000 0v table 1 binary code table (0v to 2v ref output), gain = 2 power on reset an internal power-on-reset circuit resets the dac register to all 0s on power-up. buffer amplifier the output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k w load with a 100pf load capacitance. hardware configuration options the WM2639 has one configuration option that is controlled by a device pin. dac update the nldac pin (pin 16) can be held high to prevent word writes from updating the dac latch. by writing the new value to the dac then pulling nldac low, the new dac code is loaded into the dac latch. parallel interface the device registers data on the positive edge of nwe (pin 17). it must be enabled with ncs (pin 18) low. whether the data is written to the dac holding latch or the control register, depends on the state of input pin reg (pin 15). reg = 0 selects the dac holding latch, reg = 1 selects the control register.
production data WM2639 wolfson microelectronics ltd production data rev 1.0 july 1999 9 software configuration options data format the WM2639 writes data either to the dac holding latch or to the control register depending on the state of input pin reg. reg (pin 15) data destination 0 dac holding latch 1 control register d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x ref1 ref0 x pwr spd table 1 register bits programmable settling time settling time is a software selectable 3.5 m s or 1 m s, typical to within 0.5lsb of final value. this is controlled by the value of spd ? bit d0. a one defines a settling time of 1 m s, a zero (default) defines a settling time of 3.5 m s. programmable power down the power down function can be controlled by pwr. a zero configures the device as active, or fully powered up, a one configures the device into power down mode. when the power down function is released the device reverts to the dac code set prior to power down. programmable internal reference the reference can be sourced internally or externally under software control. if an external reference voltage is applied to the ref pin, the device must be configured to accept this. if an external reference is selected, the reference voltage input is buffered which makes the dac input resistance independent of code. the ref pin has an input resistance of 10m w and an input capacitance of typically 55pf. the reference voltage determines the dac full-scale output. if an internal reference is selected, a voltage of 1.024v or 2.048 is available. the internal reference can source up to 1ma and can therefore be used as an external system reference. ref1 ref0 reference 0 0 external (default) 0 1 1.024v 1 0 2.048v 1 1 external table 2 programmable internal reference
WM2639 production data wolfson microelectronics ltd production data rev 1.0 july 1999 10 package dimensions q q c l gauge plane 0.25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.25mm. d. meets jedec.95 mo-153, variation = ac. refer to this specification for further details. dm008.c dt: 20 pin tssop ( 6.5 x 4.4 x 1.0 mm ) symbols dimensions (mm) min nom max a ----- ----- 1.20 a 1 0.05 ----- 0.15 a 2 0.80 1.00 1.05 b 0.19 ----- 0.30 c 0.09 ----- 0.20 d 6.40 6.50 6.60 e 0.65 bsc e 6.4 bsc e 1 4.30 4.40 4.50 l 0.45 0.60 0.75 q 0 o 8 ref: a a2 a1 seating plane -c- 0.05 c 11 20 e1 e e b 10 1 d
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